1. Field of the Invention
The present invention relates to a semiconductor device, in particular, to an ESD protection circuit for protecting an input terminal of a semiconductor device.
2. Description of the Related Art
An example for an ESD protection circuit of a conventional semiconductor device is given and explained. FIG. 5 is a circuit diagram showing an ESD protection circuit for an input terminal of a conventional semiconductor device.
The resistors 92 and 93 serially connected to the input terminal 91 slow down the propagation of a surge from the input terminal 11 to the internal circuit, and prevent the flow of rush current into the internal circuit. The PMOS transistor 94 and the NMOS transistor 95, which are normally off, discharge the excess current to the power supply terminal or to the ground terminal respectively through the avalanche breakdown of the PN junction at the drain when the surge invades from the input terminal 91, protecting the internal circuit from the excess current generated by the surge (see, for example, Japanese Published Patent Application H11-121750).
In the conventional protection circuit a PMOS transistor or an NMOS transistor having an area large enough to flow a large current caused by the surge has to be arranged for each input terminal between the power supply terminal and input terminal or between the ground terminal and the input terminal, respectively, which sometimes becomes an obstacle in scaling down the IC chip area of the semiconductor device.